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Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet CF52002-2.1 Features Enhanced configuration devices include EPC4, EPC8, and EPC16 devices Single-chip configuration solution for Stratix(R) series, CycloneTM series, APEXTM II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), MercuryTM, ACEX(R) 1K, and FLEX(R) 10K (FLEX 10KE and FLEX 10KA) devices Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage On-chip decompression feature almost doubles the effective configuration density Standard flash die and a controller die combined into single stacked chip package External flash interface supports parallel programming of flash and external processor access to unused portions of memory Flash memory block/sector protection capability via external flash interface Supported in EPC16 and EPC4 devices Page mode support for remote and local reconfiguration with up to eight configurations for the entire system Compatible with Stratix series Remote System Configuration feature Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs Pin-selectable 2-ms or 100-ms power-on reset (POR) time Configuration clock supports programmable input source and frequency synthesis Multiple configuration clock sources supported (internal oscillator and external clock input pin) External clock source with frequencies up to 133 MHz Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of 33, 50, and 66 MHz Clock synthesis supported via user programmable divide counter Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA(R) packages Vertical migration between all devices supported in the 100-pin PQFP package Supply voltage of 3.3 V (core and I/O) Altera Corporation August 2005 2-1 Functional Description Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification Supports ISP via Jam Standard Test and Programming Language (STAPL) Supports Joint Test Action Group (JTAG) boundary scan nINIT_CONF pin allows private JTAG instruction to initiate FPGA configuration Internal pull-up resistor on nINIT_CONF always enabled User programmable weak internal pull-up resistors on nCS and OE pins Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines Standby mode with reduced power consumption f For more information on FPGA configuration schemes and advanced features, refer to the appropriate FPGA family chapter in the Configuration Handbook. The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete. 1 The external flash interface is currently supported in the EPC16 and EPC4 devices. For information on using this feature in the EPC8 device, contact Altera Applications. Functional Description The enhanced configuration device has a 3.3-V core and I/O interface. The controller chip is a synchronous system that implements the various interfaces and features. Figure 2-1 shows a block diagram of the enhanced configuration device. The controller chip features three separate interfaces: A configuration interface between the controller and the Altera FPGA(s) A JTAG interface on the controller that enables in-system programmability (ISP) of the flash memory An external flash interface that the controller shares with an external processor, or FPGA implementing a Nios(R) embedded processor (interface available after ISP and configuration) 2-2 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Figure 2-1. Enhanced Configuration Device Block Diagram JTAG/ISP Interface Enhanced Configuration Device Shared Flash Interface Flash Controller FPGA Shared Flash Interface The enhanced configuration device features multiple configuration schemes. In addition to supporting the traditional passive serial (PS) configuration scheme for a single device or a serial device chain, the enhanced configuration device features concurrent configuration and parallel configuration. With the concurrent configuration scheme, up to eight PS device chains can be configured simultaneously. In the FPP configuration scheme, 8-bits of data are clocked into the FPGA each cycle. These schemes offer significantly reduced configuration times over traditional schemes. Furthermore, the enhanced configuration device features a dynamic configuration or page mode feature. This feature allows you to dynamically reconfigure all the FPGAs in your system with new images stored in the configuration memory. Up to eight different system configurations or pages can be stored in memory and selected using the PGM[2..0] pins. Your system can be dynamically reconfigured by selecting one of the eight pages and initiating a reconfiguration cycle. This page mode feature combined with the external flash interface allows remote and local updates of system configuration data. The enhanced configuration devices are compatible with the Stratix Remote System Configuration feature. Altera Corporation August 2005 2-3 Configuration Handbook, Volume 2 Functional Description 1 For more information on Stratix Remote System Configuration, refer to the Using Remote System Configuration with Stratix & Stratix GX Devices chapter of the Stratix Device Handbook. Other user programmable features include: Real-time decompression of configuration data Programmable configuration clock (DCLK) Flash ISP Programmable power-on-reset delay (PORSEL) FPGA Configuration FPGA configuration is managed by the configuration controller chip. This process includes reading configuration data from the flash memory, decompressing it if necessary, transmitting configuration data via the appropriate DATA[] pins, and handling errors conditions. After POR, the controller determines the user-defined configuration options by reading its option bits from the flash memory. These options include the configuration scheme, configuration clock speed, decompression, and configuration page settings. The option bits are stored at flash address location 0x8000 (word address) and occupy 512-bits or 32-words of memory. These options bits are read using the internal flash interface and the default 10 MHz internal oscillator. After obtaining the configuration settings, it checks if the FPGA is ready to accept configuration data by monitoring the nSTATUS and CONF_DONE lines. When the FPGA is ready (nSTATUS is high and CONF_DONE is low), the controller begins data transfer using the DCLK and DATA[] output pins. The controller selects the configuration page to be transmitted to the FPGA(s) by sampling its PGM[2..0] pins after POR or reset. The function of the configuration unit is to transmit decompressed data to the FPGA, depending on the configuration scheme. The enhanced configuration device supports four concurrent configuration modes, with n = 1, 2, 4, or 8 (where n is the number of bits that are sent per DCLK cycle on the DATA[n] lines). The value n=1 corresponds to the traditional PS configuration scheme. The values n=2, 4, and 8 correspond to concurrent configuration of 2, 4, or 8 different PS configuration chains, respectively. Additionally, the FPGA can be configured in FPP mode, where eight bits of DATA are clocked into the FPGA per DCLK cycle. Depending on the configuration bus width (n), the circuit shifts uncompressed configuration data to the valid DATA[n] pins. Unused DATA[] pins drive low. 2-4 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet In addition to transmitting configuration data to the FPGAs, the configuration circuit is also responsible for pausing configuration whenever there is insufficient data available for transmission. This occurs when the flash read bandwidth is lower than the configuration write bandwidth. Configuration is paused by stopping the DCLK to the FPGA, when waiting for data to be read from the flash or for data to be decompressed. This technique is called "Pausing DCLK." The enhanced configuration device flash memories feature a 90-ns access time (approximately 10 MHz). Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to high configuration write bandwidths. For instance, 100-MHz Stratix FPP configuration requires data at the rate of 800 Mbps (8-bit DATA[] bus at 100 MHz). This is much higher than the 160 Mbps the flash memory can support, and is the limiting factor for configuration time. Compression increases the effective flash read bandwidth since the same amount of configuration data takes up less space in the flash memory after compression. Since Stratix configuration data compression ratios are approximately two, the effective read bandwidth doubles to about 320 Mbps. Finally, the configuration controller also manages errors during configuration. A CONF_DONE error occurs when the FPGA does not deassert its CONF_DONE signal within 64 DCLK cycles after the last bit of configuration data is transmitted. When a CONF_DONE error is detected, the controller pulses the OE line low, which pulls nSTATUS low and triggers another configuration cycle. A cyclic redundancy check (CRC) error occurs when the FPGA detects corruption in the configuration data. This corruption could be a result of noise coupling on the board such as poor signal integrity on the configuration signals. When this error is signaled by the FPGA (by driving the nSTATUS line low), the controller stops configuration. If the Auto-Restart Configuration After Error option is enabled in the FPGA, it releases its nSTATUS signal after a reset time-out period and the controller attempts to reconfigure the FPGA. After the FPGA configuration process is complete, the controller drives DCLK low and the DATA[] pins high. Additionally, the controller tristates its internal interface to the flash memory, enables the weak internal pull-ups on the flash address and control lines, and enables bus-keep circuits on flash data lines. The following sections briefly describe the different configuration schemes supported by the enhanced configuration device: FPP, PS, and concurrent configuration. Altera Corporation August 2005 2-5 Configuration Handbook, Volume 2 Functional Description f For detailed information on using these schemes to configure your Altera FPGA, refer to the appropriate FPGA family chapter in the Configuration Handbook. Configuration Signals Table 2-3 lists the configuration signal connections between the enhanced configuration device and Altera FPGAs. Table 2-3. Configuration Signals Enhanced Configuration Device Pin DATA[] Altera FPGA Pin DATA[] Description Configuration data transmitted from the configuration device to the FPGA, which is latched on the rising edge of DCLK. Configuration device generated clock used by the FPGA to latch configuration data provided on the DATA[] pins. Open-drain output from the configuration device that is used to initiate FPGA reconfiguration using the initiate configuration (INIT_CONF) JTAG instruction. This connection is not needed if the INIT_CONF JTAG instruction is not needed. If nINIT_CONF is not connected to nCONFIG, nCONFIG must be tied to VCC either directly or through a pull-up resistor. Open-drain bidirectional configuration status signal, which is driven low by either device during POR and to signal an error during configuration. Low pulse on OE resets the enhanced configuration device controller. DCLK DCLK nINIT_CONF nCONFIG OE nSTATUS nCS CONF_DONE Configuration done output signal driven by the FPGA. 2-6 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Fast Passive Parallel Configuration Stratix series and APEX II devices can be configured using the enhanced configuration device in FPP mode. In this mode, the enhanced configuration device sends a byte of data on the DATA[7..0] pins, which connect to the DATA[7..0] input pins of the FPGA, per DCLK cycle. Stratix series and APEX II FPGAs receive byte-wide configuration data per DCLK cycle. Figure 2-2 shows the enhanced configuration device in FPP configuration mode. In this figure, the external flash interface is not used and hence most flash pins are left unconnected (with the few noted exceptions). For specific details on configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the Configuration Handbook. Altera Corporation August 2005 2-7 Configuration Handbook, Volume 2 Functional Description Figure 2-2. FPP Configuration VCC (1) VCC (1) Stratix Series or APEX II Device n (6) MSEL DCLK DATA[7..0] nSTATUS CONF_DONE nCONFIG (1) VCC N.C. nCEO nCE Enhanced Configuration Device (3) (3) WE#C WE#F RP#C RP#F DCLK A[20..0] DATA[7..0] OE (3) RY/BY# nCS (3) CE# nINIT_CONF (2) OE# DQ[15..0] WP# BYTE# (5) TM1 VCC (1) VCCW PORSEL PGM[2..0] TMO EXCLK (4) (4) (4) N.C. N.C. N.C. N.C. N.C. GND GND C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) A0-F A1-F A15-F A16-F Notes to Figure 2-2: (1) (2) The VCC should be connected to the same supply voltage as the configuration device. The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor. The enhanced configuration devices' OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus(R) II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. For PORSEL, PGM[], and EXCLK pin connections, refer to Table 2-9. In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to F-A16, and BYTE# to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to GND, and WP# to VCC. Connect the FPGA MSEL[] input pins to select the FPP configuration mode. For details, refer to the appropriate FPGA family chapter in the Configuration Handbook. (3) (4) (5) (6) Multiple FPGAs can be configured using a single enhanced configuration device in FPP mode. In this mode, multiple Stratix series and/or APEX II FPGAs are cascaded together in a daisy chain. 2-8 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet After the first FPGA completes configuration, its nCEO pin asserts to activate the second FPGA's nCE pin, which prompts the second device to start capturing configuration data. In this setup, the FPGAs CONF_DONE pins are tied together, and hence all devices initialize and enter user mode simultaneously. If the enhanced configuration device or one of the FPGAs detects an error, configuration stops (and simultaneously restarts) for the whole chain because the nSTATUS pins are tied together. 1 While Altera FPGAs can be cascaded in a configuration chain, the enhanced configuration devices cannot be cascaded to configure larger devices/chains. f For configuration schematics and more information on multi-device FPP configuration, refer to the appropriate FPGA family chapter in the Configuration Handbook. Passive Serial Configuration Stratix series, Cyclone series, APEX II, APEX 20KC, APEX 20KE, APEX 20K, and FLEX 10K devices can be configured using enhanced configuration devices in the PS mode. This mode is similar to the FPP mode, with the exception that only one bit of data (DATA[0]) is transmitted to the FPGA per DCLK cycle. The remaining DATA[7..1] output pins are unused in this mode and drive low. The configuration schematic for PS configuration of a single FPGA or single serial chain is identical to the FPP schematic (with the exception that only DATA[0] output from the enhanced configuration device connects to the FPGA DATA0 input pin; remaining DATA[7..1] pins are left floating). f For configuration schematics and more information on multi-device PS configuration, refer to the appropriate FPGA family chapter in the Configuration Handbook. Concurrent Configuration The enhanced configuration device supports concurrent configuration of multiple FPGAs (or FPGA chains) in PS mode. Concurrent configuration is when the enhanced configuration device simultaneously outputs n bits of configuration data on the DATA[n-1..0] pins (n = 1, 2, 4, or 8), and each DATA[] line serially configures a different FPGA (chain). The number of concurrent serial chains is user-defined via the Quartus II software and can be any number between 1 and 8. For example, three concurrent chains you can select the 4-bit PS mode, and connect the least Altera Corporation August 2005 2-9 Configuration Handbook, Volume 2 Functional Description significant DATA bits to the FPGAs or FPGA chains. Leave the most significant DATA bit (DATA[3]) unconnected. Similarly, for 5-, 6- or 7-bit concurrent chains you can select the 8-bit PS mode. Figure 2-3 shows the schematic for configuring multiple FPGAs concurrently in the PS mode using an enhanced configuration device. f For specific details on configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the Configuration Handbook. 2-10 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Figure 2-3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8) VCC (1) VCC (1) Enhanced Configuration Device WE#C RP#C DCLK DATA0 DATA1 FPGA0 n (6) MSEL DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCE N.C. nCEO (3) (3) WE#F RP#F A[20..0] RY/BY# CE# OE# DQ[15..0] N.C. N.C. N.C. N.C. N.C. OE (3) nCS (3) FPGA1 n (6) MSEL DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCE N.C. nCEO GND nINIT_CONF (2) DATA 7 (1) VCC VCCW WP# BYTE# (5) TM1 PORSEL PGM[2..0] EXCLK VCC (1) GND (4) (4) (4) FPGA7 n (6) MSEL DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCE N.C. nCEO GND TMO GND C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) A0-F A1-F A15-F A16-F Notes to Figure 2-3: (1) (2) Connect VCC to the same supply voltage as the configuration device. The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor. The enhanced configuration devices' OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. For PORSEL, PGM[], and EXCLK pin connections, refer to Table 2-9. In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to F-A16, and BYTE# to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to GND, and WP# to VCC. Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the Configuration Handbook. (3) (4) (5) (6) Altera Corporation August 2005 2-11 Configuration Handbook, Volume 2 Functional Description Table 2-4 summarizes the concurrent PS configuration modes supported in the enhanced configuration device. Table 2-4. Enhanced Configuration Devices in PS Mode Mode Name Passive serial mode Multi-device passive serial mode Multi-device passive serial mode Multi-device passive serial mode Note to Table 2-4: (1) This is the number of valid DATA outputs for each configuration mode. Mode (n =) (1) Used Outputs 1 2 4 8 DATA0 Unused Outputs DATA[7..1] drive low DATA[1..0] DATA[7..2] drive low DATA[3..0] DATA[7..4] drive low DATA[7..0] - f For configuration schematics and more information on concurrent configuration, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. or the appropriate FPGA family chapter in the Configuration Handbook. External Flash Interface The enhanced configuration devices support external FPGA or processor access to its flash memory. The unused portions of the flash memory can be used by the external device to store code or data. This interface can also be used in systems that implement remote configuration capabilities. Configuration data within a particular configuration page can be updated via the external flash interface and the system could be reconfigured with the new FPGA image. This interface is also useful to store Nios boot code and/or application code. f For more information on the Stratix remote configuration feature, refer to the Using Remote System Configuration with Stratix & Stratix GX Devices chapter of the Stratix Device Handbook. The address, data, and control ports of the flash memory are internally connected to the enhanced configuration device controller and to external device pins. An external source can drive these external device pins to access the flash memory when the flash interface is available. This external flash interface is a shared bus interface with the configuration controller chip. The configuration controller is the primary bus master. Since there is no bus arbitration support, the external device can only access the flash interface when the controller has tri-stated its 2-12 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet internal interface to the flash. Simultaneous access by the controller and the external device will cause contention, and result in configuration and programming failures. Since the internal flash interface is directly connected to the external flash interface pins, controller flash access cycles will toggle the external flash interface pins. The external device must be able to tri-state its flash interface during these times and ignore transitions on the flash interface pins. 1 The external flash interface signals cannot be shared between multiple enhanced configuration devices because this causes contention during in-system programming and configuration. During these times, the controller chips inside the enhanced configuration devices are actively accessing flash memory. Therefore, enhanced configuration devices do not support shared flash bus interfaces. The enhanced configuration device controller chip accesses flash memory during: FPGA configuration--reading configuration data from flash JTAG-based flash programming--storing configuration data in flash At POR--reading option bits from flash During these times, the external FPGA/processor must tri-state its interface to the flash memory. After configuration and programming, the enhanced configuration device's controller tri-states the internal interface and goes into an idle mode. To interrupt a configuration cycle in order to access the flash via the external flash interface, the external device can hold the FPGA's nCONFIG input low. This keeps the configuration device in reset by holding the nSTATUS-OE line low, allowing external flash access. f For further details on the software support for the external flash interface feature, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. For details on flash commands, timing, memory organization, and write protection features, refer to the appropriate flash data sheet (Sharp LHF16306 for EPC16 devices and Micron MT28F400B3 for EPC4 devices) on the Altera web site at www.altera.com. Figure 2-4 shows a FPP configuration schematic with the external flash interface being used. Altera Corporation August 2005 2-13 Configuration Handbook, Volume 2 Functional Description Figure 2-4. FPP Configuration with External Flash Interface Note (1) VCC Stratix Series or APEX II Device n MSEL DCLK DATA[7..0] nSTATUS CONF_DONE nCONFIG VCC Enhanced Configuration Device WE#C WE#F RP#C RP#F DCLK DATA[7..0] A[20..0] (2) OE RY/BY# nCS CE# nINIT_CONF OE# DQ[15..0] PLD or Processor WE# RP# A[20..0] RY/BY# CE# OE# DQ[15..0] VCC N.C. nCEO nCE VCC WP# BYTE# (3) TM1 GND VCCW PORSEL PGM[2..0] TMO EXCLK (4) (4) (4) GND C-A0 (3) C-A1 (3) C-A15 (3) C-A16 (3) A0-F A1-F A15-F A16-F Notes to Figure 2-4: (1) (2) (3) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications. Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins. In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to F-A16, and BYTE # to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to GND, and WP# to VCC. For PORSEL, PGM[], and EXCLK pin connections, refer to Table 2-9. (4) Dynamic Configuration (Page Mode) The dynamic configuration or page mode feature allows the enhanced configuration device to store up to eight different sets of designs for all the FPGAs in your system. You can then choose which page (set of configuration files) the enhanced configuration device should use for FPGA configuration. 2-14 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Dynamic configuration or the page mode feature enables you to store a minimum of two pages: a factory default or fail-safe configuration, and an application configuration. The fail-safe configuration page could be programmed during system production, while the application configuration page could support remote or local updates. These remote updates could add or enhance system features and performance. However, with remote update capabilities comes the risk of possible corruption of configuration data. In the event of such a corruption, the system could automatically switch to the fail-safe configuration and avoid system downtime. The enhanced configuration device page mode feature works with the Stratix Remote System Configuration feature, to enable intelligent remote updates to your systems. f For more information on remotely updating Stratix FPGAs, refer to Using Remote System Configuration with Stratix & Stratix GX Devices in the Stratix Device Handbook. The three PGM[2..0] input pins control which page is used for configuration, and these pins are sampled at the start of each configuration cycle when OE goes high. The page mode selection allows you to dynamically reconfigure the functionality of your FPGA(s) by switching the PGM[2..0] pins and asserting nCONFIG. Page 0 is defined as the default page and the PGM[2] pin is the most significant bit (MSB). 1 The PGM[2..0] input pins must not be left floating on your board, regardless of whether this feature is used or not. When this feature is not used, connect the PGM[2..0] pins to GND to select the default page 000. The enhanced configuration device pages are dynamically sized regions in memory. The start address and length of each page is programmed into the option bit space of the flash memory during initial programming. All subsequent configuration cycles will sample the PGM[] pins and use the option bit information to jump to the start of the corresponding configuration page. Each page must have configuration files for all FPGAs in your system that are connected to that enhanced configuration device. For example, if your system requires three configuration pages and includes two FPGAs, each page will store two SRAM Object Files (.sof) for a total of six SOFs in the configuration device. Altera Corporation August 2005 2-15 Configuration Handbook, Volume 2 Functional Description Furthermore, all enhanced configuration device configuration schemes (PS, FPP, and concurrent PS) are supported with the page mode feature. The number of pages and/or devices that can be configured using a single enhanced configuration device is only limited by the size of the flash memory. f For detailed information on the page mode feature implementation and programming file generation steps using Quartus II software, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. Real-Time Decompression Enhanced configuration devices support on-chip real time decompression of configuration data. FPGA configuration data is compressed by the Quartus II software and stored in the enhanced configuration device. During configuration, the decompression engine inside the enhanced configuration device will decompress or expand configuration data. This feature increases the effective configuration density of the enhanced configuration device up to 7, 15, or 30 Mbits in the EPC4, EPC8, and EPC16, respectively. The enhanced configuration device also supports a parallel 8-bit data bus to the FPGA to reduce configuration time. However, in some cases, the FPGA data transfer time is limited by the flash read bandwidth. For example, when configuring an APEX II device in FPP (byte-wide data per cycle) mode at a configuration speed of 66 MHz, the FPGA write bandwidth is equal to 8 bits x 66 MHz = 528 Mbps. The flash read interface, however, is limited to approximately 10 MHz (since the flash access time is ~90 ns). This translates to a flash read bandwidth of 16 bits x 10 MHz = 160 Mbps. Hence, the configuration time is limited by the flash read time. When configuration data is compressed, the amount of data that needs to be read out of the flash is reduced by about 50%. If 16 bits of compressed data yields 30 bits of uncompressed data, the flash read bandwidth increases to 30 bits x 10 MHz = 300 Mbps, reducing overall configuration time. You can enable the controller's decompression feature in the Quartus II software, Configuration Device Options window by turning on Compression Mode. 2-16 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet 1 The decompression feature supported in the enhanced configuration devices is different from the decompression feature supported by the Stratix II FPGAs and the Cyclone series. When configuring Stratix II FPGAs or the Cyclone series using enhanced configuration devices, Altera recommends enabling decompression in Stratix II FPGAS or the Cyclone series only for faster configuration. The compression algorithm used in Altera devices is optimized for FPGA configuration bitstreams. Since FPGAs have several layers of routing structures (for high performance and easy routability), large amounts of resources go unused. These unused routing and logic resources as well as un-initialized memory structures result in a large number of configuration RAM bits in the disabled state. Altera's proprietary compression algorithm takes advantage of such bitstream qualities. The general guideline for effectiveness of compression is the higher the device logic/routing utilization, the lower the compression ratio (where compression ratio is defined as original bitstream size divided by the compressed bit-stream size). For Stratix designs, based on a suite of designs with varying amounts of logic utilization, the minimum compression ratio was observed to be 1.9 or a ~47% size reduction for these designs. Table 2-5 shows sample compression ratios from a suite of Stratix designs. These numbers serve as a guideline (not a specification) to help you allocate sufficient configuration memory to store compressed bitstreams. Table 2-5. Stratix Compression Ratios Note (1) Minimum Logic Utilization Compression Ratio % Size Reduction Note to Table 2-5: (1) These numbers are preliminary. They are intended to serve as a guideline, not a specification. Average 64% 2.3 57% 98% 1.9 47% Altera Corporation August 2005 2-17 Configuration Handbook, Volume 2 Functional Description Programmable Configuration Clock The configuration clock (DCLK) speed is user programmable. One of two clock sources can be used to synthesize the configuration clock; a programmable oscillator or an external clock input pin (EXCLK). The configuration clock frequency can be further synthesized using the clock divider circuitry. This clock can be divided by the N counter to generate your DCLK output. The N divider supports all integer dividers between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock divisions other than non-integer divisions is 50% (for the noninteger dividers, the duty cycle will not be 50%). See Figure 2-5 for a block diagram of the clock divider unit. Figure 2-5. Clock Divider Unit Configuration Device Clock Divider Unit External Clock (Up to 133 MHz) 10 MHz 33 MHz 50 MHz 66 MHz Internal Oscillator Divide by N DCLK The DCLK frequency is limited by the maximum DCLK frequency the FPGA supports. f The maximum DCLK input frequency supported by the FPGA is specified in the appropriate FPGA family chapter in the Configuration Handbook. 2-18 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet The controller chip features a programmable oscillator that can output four different frequencies. The various settings generate clock outputs at frequencies as high as 10, 33, 50, and 66 MHz, as shown in Table 2-6. Table 2-6. Internal Oscillator Frequencies Frequency Setting 10 33 50 66 Min (MHz) 6.4 21.0 32.0 42.0 Typ (MHz) 8.0 26.5 40.0 53.0 Max (MHz) 10.0 33.0 50.0 66.0 Clock source, oscillator frequency, and clock divider (N) settings can be made in the Quartus II software, by accessing the Configuration Device Options inside the Device Settings window or the Convert Programming Files window. The same window can be used to select between the internal oscillator and the external clock (EXCLK) input pin as your configuration clock source. The default setting selects the internal oscillator at the 10 MHz setting as the clock source, with a divide factor of 1. f For more information on making the configuration clock source, frequency, and divider settings, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. Flash In-System Programming (ISP) The flash memory inside enhanced configuration devices can be programmed in-system via the JTAG interface and the external flash interface. JTAG-based programming is facilitated by the configuration controller in the enhanced configuration device. External flash interface programming requires an external processor or FPGA to control the flash. 1 The enhanced configuration device flash memory supports 100,000 erase cycles. JTAG-based Programming The IEEE Std. 1149.1 JTAG Boundary Scan is implemented in enhanced configuration devices to facilitate the testing of its interconnection and functionality. Enhanced configuration devices also support the ISP mode. The enhanced configuration device is compliant with the IEEE Std. 1532 draft 2.0 specification. Altera Corporation August 2005 2-19 Configuration Handbook, Volume 2 Functional Description The JTAG unit of the configuration controller communicates directly with the flash memory. The controller processes the ISP instructions and performs the necessary flash operations. The enhanced configuration devices support a maximum JTAG TCK frequency of 10 MHz. During JTAG-based ISP, the external flash interface is not available. Before the JTAG interface programs the flash memory, an optional JTAG instruction (PENDCFG) can be used to assert the FPGA's nCONFIG pin (via the nINIT_CONF pin). This will keep the FPGA in reset and terminate any internal flash access. This function prevents contention on the flash pins when both JTAG ISP and an external FPGA/processor try to access the flash simultaneously. The nINIT_CONF pin is released when the Initiate Configuration (nINIT_CONF) JTAG instruction is updated. As a result, the FPGA is configured with the new configuration data stored in flash. This function can be added to your programming file in the Quartus II software by enabling the Initiate configuration after programming option in the Programmer options window (Options menu). Programming via External Flash Interface This method allows parallel programming of the flash memory (using the 16-bit data bus). An external processor or FPGA acts as the flash controller and has access to programming data (via a communication link such as UART, Ethernet, and PCI). In addition to the program, erase, and verify operations, the external flash interface supports block/sector protection instructions. f For information on protection commands, areas, and lock bits, refer to the appropriate flash memory data sheet (Sharp LHF16506 for EPC16 devices and Micron MT28F400B3 for EPC4 devices) on the Altera web site at www.altera.com. External flash interface programming is only allowed when the configuration controller has relinquished flash access (by tri-stating its internal interface). If the controller has not relinquished flash access (during configuration or JTAG-based ISP), you must hold the controller in reset before initiating external programming. The controller can be reset by holding the FPGA nCONFIG line at a logic low level. This keeps the controller in reset by holding the nSTATUS-OE line low, allowing external flash access. 1 If initial programming of the enhanced configuration device is done in-system via the external flash interface, the controller must be kept in reset by driving the FPGA nCONFIG line low to prevent contention on the flash interface. 2-20 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Pin Description Tables 2-7 through 2-9 describe the enhanced configuration device pins. These tables include configuration interface pins, external flash interface pins, JTAG interface pins, and other pins. Table 2-7. Configuration Interface Pins Pin Name Pin Type Description This is the configuration data output bus. DATA changes on each falling edge of DCLK. DATA is latched into the FPGA on the rising edge of DCLK. The DCLK output pin from the enhanced configuration device serves as the FPGA configuration clock. DATA is latched by the FPGA on the rising edge of DCLK. The nCS pin is an input to the enhanced configuration device and is connected to the FPGA's CONF_DONE signal for error detection after all configuration data is transmitted to the FPGA. The FPGA will always drive nCS and OE low when nCONFIG is asserted. This pin contains a programmable internal weak pull-up resistor that can be disabled/enabled in the Quartus II software through the Disable nCS and OE pull-ups on configuration device option. The nINIT_CONF pin can be connected to the nCONFIG pin on the FPGA to initiate configuration from the enhanced configuration device via a private JTAG instruction. This pin contains an internal weak pull-up resistor that is always active. The INIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a pull-up resistor. This pin is driven low when POR is not complete. A user-selectable 2-ms or 100-ms counter holds off the release of OE during initial power up to permit voltage levels to stabilize. POR time can be extended by externally holding OE low. OE is connected to the FPGA nSTATUS signal. After the enhanced configuration device controller releases OE, it waits for the nSTATUS-OE line to go high before starting the FPGA configuration process. This pin contains a programmable internal weak pull-up resistor that can be disabled/enabled in the Quartus II software through the Disable nCS and OE pull-ups on configuration device option. DATA[7..0] Output DCLK Output nCS Input nINIT_CONF Open-Drain Output OE Open-Drain Bidirectional Altera Corporation August 2005 2-21 Configuration Handbook, Volume 2 Pin Description Table 2-8. External Flash Interface Pins (Part 1 of 2) Pin Name A[20..0] Pin Type Input Description These pins are the address input to the flash memory for read and write operations. The addresses are internally latched during a write cycle. When the external flash interface is not used, leave these pins floating (with the few exceptions noted below). These flash address, data, and control pins are internally connected to the configuration controller. In the 100-pin PQFP package, four address pins (A0, A1, A15, A16) are not internally connected to the controller. These loop back connections must be made on the board between the C-A[] and F-A[] pins even when not using the external flash interface. All other address pins are connected internal to the package. All address pins are connected internally in the 88-pin Ultra FineLine BGA package. Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices are no-connects. These pins should be left floating on the board. DQ[15..0] Bidirectional This is the flash data bus interface between the flash memory and the controller. The controller or an external source drives DQ[15..0] during the flash command and the data write bus cycles. During the data read cycle, the flash memory drives the DQ[15..0] to the controller or external device. Leave these pins floating on the board when the external flash interface is not used. CE# Input Active low flash input pin that activates the flash memory when asserted. When it is high, it deselects the device and reduces power consumption to standby levels. This flash input pin is internally connected to the controller. Leave this pin floating on the board when the external flash interface is not used. RP# (1) Input Active low flash input pin that resets the flash when asserted. When high, it enables normal operation. When low, it inhibits write operation to the flash memory, which provides data protection during power transitions. This flash input is not internally connected to the controller. Hence, an external loop back connection between C-RP# and F-RP# must be made on the board even when you are not using the external flash interface. When using the external flash interface, connect the external device to the RP# pin with the loop back. 2-22 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Table 2-8. External Flash Interface Pins (Part 2 of 2) Pin Name OE# Pin Type Input Description Active low flash control input that is asserted by the controller or external device during flash read cycles. When asserted, it enables the drivers of the flash output pins. Leave this pin floating on the board when the external flash interface is not used. WE# (1) Input Active low flash write strobe asserted by the controller or external device during flash write cycles. When asserted, it controls writes to the flash memory. In the flash memory, addresses and data are latched on the rising edge of the WE# pulse. This flash input is not internally connected to the controller. Hence, an external loop back connection between C-WE# and F-WE# must be made on the board even when you are not using the external flash interface. When using the external flash interface, connect the external device to the WE# pin with the loop back. WP# Input This pin is usually tied to VCC or ground on the board. The controller does not drive this pin because it could cause contention. Connection to VCC is recommended for faster block erase/programming times and to allow programming of the flash bottom boot block, which is required when programming the device using the Quartus II software. This pin should be connected to VCC even when the external flash interface is not used. VCCW Supply Block erase, full chip erase, word write, or lock bit configuration power supply. Connect this pin to the 3.3-V VCC supply, even when you are not using the external flash interface. RY/BY# Output Flash asserts this pin when a write or erase operation is complete. This pin is not connected to the controller. Leave this pin floating when the external flash interface is not used. BYTE# Input This is flash byte enable pin and is only available for enhanced configuration devices in the 100-pin PQFP package. This pin must be connected to VCC on the board even when you are not using the external flash interface (the controller uses the flash in 16-bit mode). Note to Table 2-8: (1) These pins can be driven to 12 V during production testing of the flash memory. Since the controller cannot tolerate the 12-V level, connections from the controller to these pins are not made internal to the package. Instead they are available as two separate pins. You must connect the two pins at the board level (for example, on the printed circuit board (PCB), connect the C-WE# pin from controller to F-WE# pin from the flash memory). Altera Corporation August 2005 2-23 Configuration Handbook, Volume 2 Power-On Reset (POR) Table 2-9. JTAG Interface Pins and Other Required Controller Pins Pin Name TDI Pin Type Input Description This is the JTAG data input pin. Connect this pin to VCC if the JTAG circuitry is not used. TDO Output This is the JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used (leave floating). TCK Input This is the JTAG clock pin. Connect this pin to GND if the JTAG circuitry is not used. TMS Input This is the JTAG mode select pin. Connect this pin to VCC if the JTAG circuitry is not used. PGM[2..0] Input These three input pins select one of the eight pages of configuration data to configure the FPGA(s) in the system. Connect these pins on the board to select the page specified in the Quartus II software when generating the enhanced configuration device POF. PGM[2] is the MSB. Default selection is page 0; PGM[2..0]=000. These pins must not be left floating. EXCLK Input Optional external clock input pin that can be used to generate the configuration clock (DCLK). When an external clock source is not used, connect this pin to a valid logic level (high or low) to prevent a floating input buffer. PORSEL Input This pin selects a 2-ms or 100-ms POR counter delay during power up. When PORSEL is low, POR time is 100-ms. When PORSEL is high, POR time is 2 ms. This pin must be connected to a valid logic level. TM0 TM1 Input Input For normal operation, this test pin must be connected to GND. For normal operating, this test pin must be connected to VCC. Power-On Reset (POR) The POR circuit keeps the system in reset until power supply voltage levels have stabilized. The POR time consists of the VCC ramp time and a user programmable POR delay counter. When the supply is stable and the POR counter expires, the POR circuit releases the OE pin. The POR time can be further extended by an external device by driving the OE pin low. 1 Do not execute JTAG or ISP instructions until POR is complete. 2-24 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet The enhanced configuration device supports a programmable POR delay setting. You can set the POR delay to the default 100-ms setting or reduce the POR delay to 2 ms for systems that require fast power-up. The PORSEL input pin controls this POR delay; a logic high level selects the 2-ms delay, while a logic low level selects the 100-ms delay. The enhanced configuration device can enter reset under the following conditions: The POR reset starts at initial power-up during VCC ramp-up or if VCC drops below the minimum operating condition anytime after VCC has stabilized The FPGA initiates reconfiguration by driving nSTATUS low, which occurs if the FPGA detects a CRC error or if the FPGA's nCONFIG input pin is asserted The controller detects a configuration error and asserts OE to initiate re-configuration of the Altera FPGA (for example when CONF_DONE stays low after all configuration data has been transmitted) Power Sequencing Altera requires that you power-up the FPGA's VCCINT supply before the enhanced configuration device's POR expires. Power up needs to be controlled so that the enhanced configuration device's OE signal goes high after the CONF_DONE signal is pulled low. If the EEPC device exits POR before the FPGA is powered up, the CONF_DONE signal will be high since the pull-up resistor is holding this signal high. When the enhanced configuration device exits POR, OE is released and pulled high by a pull-up resistor. Since the enhanced configuration device samples the nCS signal on the rising edge of OE, it detects a high level on CONF_DONE and enters an idle mode. DATA and DCLK outputs will not toggle in this state and configuration will not begin. The enhanced configuration device will only exit this mode if it is powered down and then powered up correctly. 1 To ensure the enhanced configuration device enters configuration mode properly, you need to ensure that the FPGA completes power-up before the enhanced configuration device exits POR. The pin-selectable POR time feature is useful for ensuring this power-up sequence. The enhanced configuration device has two POR settings, 2 ms when PORSEL is set to a high level and 100 ms when PORSEL is set to a low level. For more margin, the 100-ms setting can be selected to allow the FPGA to power-up before configuration is attempted. Altera Corporation August 2005 2-25 Configuration Handbook, Volume 2 Programming & Configuration File Support Alternatively, a power monitoring circuit or a power good signal can be used to keep the FPGA's nCONFIG pin asserted low until both supplies have stabilized. This ensures the correct power up sequence for successful configuration. Programming & Configuration File Support f The Quartus II development software provides programming support for the enhanced configuration device and automatically generates the POF files for the EPC4, EPC8, and EPC16 devices. In a multi-device project, the software can combine the SOF files for multiple Stratix series, Cyclone series, APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K FPGAs into one programming file for the enhanced configuration device. Refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook or the Software Settings section in the Configuration Handbook for details on generating programming files. Enhanced configuration devices can be programmed in-system through its industry-standard 4-pin JTAG interface. The ISP feature in the enhanced configuration device provides ease in prototyping and updating FPGA functionality. After programming an enhanced configuration device in-system, FPGA configuration can be initiated by including the enhanced configuration device's JTAG INIT_CONF instruction (Table 2-10). The ISP circuitry in the enhanced configuration device is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard that allows concurrent ISP between devices from multiple vendors. Table 2-10. Enhanced Configuration Device JTAG Instructions (Part 1 of 2) JTAG Instruction OPCODE Description Note (1) SAMPLE/PRELOAD 00 0101 0101 Allows a snapshot of the state of the enhanced configuration device pins to be captured and examined during normal device operation and permits an initial data pattern output at the device pins. EXTEST 00 0000 0000 Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing results at the input pins. 11 1111 1111 Places the 1-bit bypass register between the TDI and the TDO pins, which allow the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. BYPASS 2-26 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Table 2-10. Enhanced Configuration Device JTAG Instructions (Part 2 of 2) JTAG Instruction IDCODE Note (1) OPCODE Description 00 0101 1001 Selects the device IDCODE register and places it between TDI and TDO, allowing the device IDCODE to be serially shifted out to TDO. The device IDCODE for all enhanced configuration devices is the same and shown below: 0100A0DDh USERCODE 00 0111 1001 Selects the USERCODE register and places it between TDI and TDO, allowing the USERCODE to be serially shifted out the TDO. The 32-bit USERCODE is a programmable user-defined pattern. 00 0110 0001 This function initiates the FPGA re-configuration process by pulsing the nINIT_CONF pin low, which is connected to the FPGA(s) nCONFIG pin(s). After this instruction is updated, the nINIT_CONF pin is pulsed low when the JTAG state machine enters Run-Test/Idle state. The nINIT_CONF pin is then released and nCONFIG is pulled high by the resistor after the JTAG state machine goes out of Run-Test/Idle state. The FPGA configuration starts after nCONFIG goes high. As a result, the FPGA is configured with the new configuration data stored in flash via ISP. This function can be added to your programming file (POF, JAM, JBC) in the Quartus II software by enabling the Initiate configuration after programming option in the Programmer options window (Options menu). 00 0110 0101 This optional function can be used to hold the nINIT_CONF pin low during JTAG-based ISP of the enhanced configuration device. This feature is useful when the external flash interface is controlled by an external FPGA/processor. This function prevents contention on the flash pins when both the controller and external device try to access the flash simultaneously. Before the enhanced configuration device's controller can access the flash memory, the external FPGA/processor needs to tri-state its interface to flash.This can be ensured by resetting the FPGA using the nINIT_CONF, which drives the nCONFIG pin and keeps the external FPGA/processor in the "reset" state. The nINIT_CONF pin is released when the Initiate Configuration (INIT_CONF) JTAG instruction is issued. INIT_CONF PENDCFG Note to Table 2-10: (1) Enhanced configuration device instruction register length is 10 and boundary scan length is 174. f For more information on the enhanced configuration device JTAG support, refer to the BSDL files provided at the Altera web site. Enhanced configuration devices can also be programmed by third-party flash programmers or on-board processors using the external flash interface. Programming files (POF) can be converted to an Intel HEX format file (.hexout) using the Quartus II Convert Programming Files utility, for use with the programmers or processors. Altera Corporation August 2005 2-27 Configuration Handbook, Volume 2 IEEE Std. 1149.1 (JTAG) Boundary-Scan You can also program the enhanced configuration devices using the Quartus II software, the Altera Programming Unit (APU), and the appropriate configuration device programming adapter. Table 2-11 shows which programming adapter to use with each enhanced configuration device. Table 2-11. Table 10. Programming Adapters Device EPC16 Package 88-pin Ultra FineLine BGA 100-pin PQFP Adapter PLMUEPC-88 PLMQEPC-100 PLMQEPC-100 PLMQEPC-100 EPC8 EPC4 100-pin PQFP 100-pin PQFP IEEE Std. 1149.1 (JTAG) Boundary-Scan The enhanced configuration device provides JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG boundaryscan testing can be performed before or after configuration, but not during configuration. Figure 2-6 shows the timing requirements for the JTAG signals. Figure 2-6. JTAG Timing Waveforms TMS TDI tJCP tJCH tJCL tJPSU tJPH TCK tJPZX tJPCO tJPXZ TDO tJSSU tJSH Signal to Be Captured Signal to Be Driven tJSZX tJSCO tJSXZ 2-28 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Table 2-12 shows the timing parameters and values for the enhanced configuration device. Table 2-12. JTAG Timing Parameters & Values Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high-impedance to valid output Update register valid output to high impedance 20 45 25 25 25 Parameter Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 ns ns ns ns ns ns ns ns Altera Corporation August 2005 2-29 Configuration Handbook, Volume 2 Timing Information Timing Information Figure 2-7 shows the configuration timing waveform when using an enhanced configuration device. Figure 2-7. Configuration Timing Waveform Using an Enhanced Configuration Device nINIT_CONF or VCC/nCONFIG OE/nSTATUS tLOE nCS/CONF_DONE DCLK DATA User I/O INIT_DONE Driven High tCE tHC tLC (1) (2) bit/byte bit/byte 1 2 bit/byte n tOE Tri-State Tri-State User Mode Notes to Figure 2-7: (1) (2) The enhanced configuration device will drive DCLK low after configuration. The enhanced configuration device will DATA[] high after configuration. Table 2-13 defines the timing parameters when using the enhanced configuration devices. f For flash memory (external flash interface) timing information, please refer to the corresponding flash data sheet on the Altera web site (Sharp LHF16J06 for EPC16 devices and Micron MT28F400B3 for EPC4 devices). Table 2-13. Enhanced Configuration Device Configuration Parameters (Part 1 of 2) Symbol fDCLK tDCLK tHC tLC tCE tOE tOH tCF (2) tDF (2) Parameter DCLK frequency DCLK period DCLK duty cycle high time DCLK duty cycle low time OE to first DCLK delay OE to first DATA available DCLK rising edge to DATA change OE assert to DCLK disable delay OE assert to DATA disable delay Condition 40% duty cycle Min Typ Max 66.7 Unit MHz ns ns ns ns ns ns ns ns 15 40% duty cycle 40% duty cycle 6 6 40 40 (1) 277 277 2-30 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Table 2-13. Enhanced Configuration Device Configuration Parameters (Part 2 of 2) Symbol tRE (3) tLOE fECLK tECLK tECLKH tECLKL tECLKR tECLKF tPOR (4) Parameter DCLK rising edge to OE OE assert time to assure reset EXCLK input frequency EXCLK input period EXCLK input duty cycle high time EXCLK input duty cycle low time EXCLK input rise time EXCLK input fall time POR time Condition Min 60 60 Typ Max Unit ns ns 40% duty cycle 7.5 40% duty cycle 40% duty cycle 133 MHz 133 MHz 2 ms 100 ms 1 70 2 100 3.375 3.375 133 MHz ns ns ns 3 3 3 120 ns ns ms ms Notes to Table 2-13: (1) (2) (3) (4) To calculate tOH, use the following equation: tOH = 0.5 (DCLK period) - 2.5 ns. This parameter is used for CRC error detection by the FPGA. This parameter is used for CONF_DONE error detection by the enhanced configuration device. The FPGA VCCINT ramp time should be less than 1-ms for 2-ms POR, and it should be less than 70 ms for 100-ms POR. Operating Conditions Tables 2-14 through 2-18 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, supply current values, and pin capacitance data for the enhanced configuration devices. Table 2-14. Enhanced Configuration Device Absolute Maximum Rating Symbol VCC VI IMAX IOUT PD TSTG TAMB TJ Parameter Supply voltage DC input voltage DC VCC or ground current DC output current, per pin Power dissipation Storage temperature Ambient temperature Junction temperature Condition With respect to ground With respect to ground Min -0.5 -0.5 Max 4.6 3.6 100 Unit V V mA mA mW C C C -25 25 360 No bias Under bias Under bias -65 -65 150 135 135 Altera Corporation August 2005 2-31 Configuration Handbook, Volume 2 Operating Conditions Table 2-15. Enhanced Configuration Device Recommended Operating Conditions Symbol VCC VI VO TA TR TF Parameter Supplies voltage for 3.3-V operation Input voltage Output voltage Operating temperature Condition Min 3.0 Max 3.6 VCC + 0.3 VCC 70 85 20 20 Unit V V V C C ns ns With respect to ground -0.3 0 For commercial use For industrial use 0 -40 Input rise time Input fall time Table 2-16. Enhanced Configuration Device DC Operating Conditions Symbol VCC VIH VIL VOH Parameter Supplies voltage to core High-level input voltage Low-level input voltage 3.3-V mode high-level TTL output voltage 3.3-V mode high-level CMOS output voltage Condition Min 3.0 2.0 Typ 3.3 Max 3.6 VCC + 0.3 0.8 Unit V V V V V IOH = -4 mA IOH = -0.1 mA IOL = -4 mA DC IOL = -0.1 mA DC VI = VCC or ground VO = VCC or ground Internal pull up (OE, nCS, nINIT, CONF) 2.4 VCC - 0.2 0.45 0.2 -10 -10 6 10 10 VOL Low-level output voltage TTL Low-level output voltage CMOS V V A A k II IOZ RCONF Input leakage current Tri-state output off-state current Configuration pins Table 2-17. Enhanced Configuration Device ICC Supply Current Values Symbol ICC0 ICC1 IC C W Note to Table 2-17: (1) For VCCW supply current information, refer to the appropriate flash memory data sheet at www.altera.com. Parameter Current (standby) VCC supply current (during configuration) VC C W supply current Condition Min Typ 50 60mA (1) Max 100 90mA (1) Unit A A 2-32 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Table 2-18. Enhanced Configuration Device Capacitance Symbol CIN COUT Parameter Input pin capacitance Output pin capacitance Condition Min Max 10 10 Unit pF pF Package The EPC16 enhanced configuration device is available in both the 88-pin Ultra FineLine BGA package and the 100-pin PQFP package. The Ultra FineLine BGA package, which is based on 0.8-mm ball pitch, maximizes board space efficiency. A board can be laid out for this package using a single PCB layer. The EPC8 and EPC4 devices are available in the 100-pin PQFP package. Enhanced configuration devices support vertical migration in the 100-pin PQFP package. Figure 2-8 shows the PCB routing for the 88-pin Ultra FineLine BGA package. The Gerber file for this layout is on the Altera web site. Altera Corporation August 2005 2-33 Configuration Handbook, Volume 2 Package Figure 2-8. PCB Routing for 88-Pin Ultra FineLine BGA Package Note (1) NC VCC A20 A11 A15 A14 A13 A12 GND DCLK DATA7 NC OE C-WE# A16 A8 A10 A9 DQ15 PGM0 DQ14 DQ7 DATA5 DATA6 (2) TCK F-WE# (2) RY/BY# nINIT CONF PGM1 DQ13 DQ6 DQ4 DQ5 DATA4 TDI GND F-RP# TM1 VCC DQ12 C-RP# VCC VCC DATA3 (2) (2) TDO WP# VCCW A19 DQ11 VCC DQ10 DQ2 DQ3 DATA2 (3) TMS NC NC PGM2 PORSEL DQ9 DQ8 DQ0 DQ1 DATA1 VCC nCS A18 A17 A7 A6 A3 A2 A1 VCC GND DATA0 NC GND EXCLK A5 A4 A0 CE# GND OE# TM0 GND NC Notes to Figure 2-8: (1) If the external flash interface feature is not used, then the flash pins should be left unconnected since they are internally connected to controller unit. The only pins that need external connections are WP#, WE#, and RP#. If the flash is being used as an external memory source, then the flash pins should be connected as outlined in the pin descriptions section. F-RP# and F-WE# are pins on the flash die. C-RP# and C-WE# are pins on the controller die. C-WE# and F-WE# should be connected together on the PCB. F-RP# and C-RP# should also be connected together on the PCB. WP# (write protection pin) should be connected to a high level (3.3 V) to be able to program the flash bottom boot block, which is required when programming the device using the Quartus II software. (2) (3) Package Layout Recommendation EPC16 and EPC8 enhanced configuration devices in the 100-pin PQFP packages have different package dimensions than other Altera 100-pin PQFP devices (including EPC4). Figure 2-9 shows the 100-pin PQFP PCB footprint specifications for enhanced configuration devices that allows for vertical migration between all three devices. These footprint dimensions are based on vendor-supplied package outline diagrams. 2-34 Configuration Handbook, Volume 2 Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Figure 2-9. Enhanced Configuration Device PCB Footprint Specifications for 100-Pin PQFP Packages Notes (1), (2) 0.65-mm pad pitch 0.325 mm 19.3 mm 0.410 mm 25.3 mm 2.4 mm 0.5 1.0 1.5 2.0 mm Notes to Figure 2-9: (1) (2) Used 0.5-mm increase for front and back of nominal foot length Used 0.3-mm increase to maximum foot width. f For package outline drawings, refer to the Altera Device Package Information Data Sheet. Altera Corporation August 2005 2-35 Configuration Handbook, Volume 2 Device Pin-Outs Device Pin-Outs Ordering Codes For pin-out information, see the Altera web site at www.altera.com. Table 2-19 shows the ordering codes for EPC4, EPC8, and EPC16 enhanced configuration devices. Table 2-19. Enhanced Configuration Device Ordering Codes Device EPC4 EPC4 EPC8 EPC8 EPC16 EPC16 EPC16 Package 100-pin PQFP 100-pin PQFP 100-pin PQFP 100-pin PQFP 100-pin PQFP 100-pin PQFP 88-pin UBGA Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Ordering Code EPC4QC100 EPC4QI100 EPC8QC100 EPC8QI100 EPC16QC100 EPC16QI100 EPC16UC88 2-36 Configuration Handbook, Volume 2 Altera Corporation August 2005 |
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